6.4 Input and Output Timing
In the following part we will examine the effect of the input and the output timing.
Input Timing: It is clear that the outputs of a circuit are not immediately available after the active clock edge. In our
example it takes roughly 0.74 ns for the outputs to appear after the active clock edge. This has to be taken into consideration
for the inputs of our circuit as well. More precisely, new inputs values will not be there immediately after the active clock
edge, a certain delay will elapse until our circuit sees valid data at its inputs.
Remove the design and start from scratch. Analyze, elaborate and constrain the design for a clock period of T = 1.0 ns,
then compile it. Continue with the constrained and compiled design, and add an input delay of 0.4 ns (Hint: man \
set_input_delay).
Output Timing: Try to imagine what happens when you sample the outputs of the design. The circuit doing the sampling
will see valid outputs only after a certain amount of time. Let us assume it will take 0.4 ns for all outputs to propagate
through the downstream circuit (i.e., the circuit connected to the outputs of our design). If this is the case, the data has to
be available at the output of our design already 0.4 ns in advance (that is: before the next active clock edge) such that the
downstream circuit is able to sample them correctly.
Student Task 9: Constrain the output timing in such a way that all outputs have settled 0.4 ns before the active
clock edge. This is to satisfy the downstream circuit that requires these 0.4 ns to sample our outputs correctly (Hint:
man set_output_delay). Check the reports now.
slack
ss
= slack
is
= A =
slack
so
= slack
io
=
As you can see, multiple timing violations occur in different paths. What has happened?
Up to now we have always looked at the most critical path in detail (every element on the path was visible). The following
command shows the worst 5 input to output paths with only their endpoints.
dcs > report_timing -from [all_inputs] -to [all_outputs] -path end -max_paths 5
Student Task 10: Report the 10 worst register state to output paths (t
so
) of the design. As you can see, there are
only a few paths violating the timing constraints. How many of them and what is the minimum/maximum slack of the
reported timing paths?
N
violations
=
slack
min
= slack
max
=
Having seen that input and output timing add some additional constraints to the design, we have to include all the constraints
prior to compilation. The SYNOPSYS DESIGN COMPILER then considers these constraints and tries to meet the defined
requirements.
Student Task 11: Remove the design and start from scratch. Analyze, elaborate, set the input and output constraints
and then compile it. Now it is once more time to investigate all the different timing paths as well as the required area.
slack
ss
= slack
is
= A =
slack
so
= slack
io
=
Are there any open violating timing paths? If you check the reports now, what differences can you see? Can you
explain them?
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