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Student Task 13: Now, redo the compilation with the constraints listed in Table 2. Furthermore, keep the previously

determined input- and output-delays. For the last two columns of Table 2, you should have a look at the t

timing

reports and write down the type of the gate at the respective output bit.

Table 2: Driving cell variations.

Speciﬁcation Results

clock period Driving Cell Load Cell Area [µm

] Gate

Out[0]

Gate

Out[7]

1.0 ns ideal ideal

1.0 ns BUFM4W 8*BUFM4W

What conclusions can you derive from the results? What effect do the constraints on the driving cell and the load

have on the performance parameters?

6.6 Area/Timing Analysis

Student Task 14: Analyze the relationship between area and timing by constraining the present design with different

clock periods. Synthesize the design with the values listed in Table 3 and complete the missing numbers. For all of the

synthesis runs, set the input and output delays to 0.1 ns and do not use any input drivers and output loads. Moreover,

assure that you use a simple compile command in order to synthesize the design. For the empty Field (big: ) in the

ﬁrst row of the table choose an appropriate value for the clock period.

Table 3: Clock period variations.

Speciﬁcation Results

Clock period T Cell Area [GE] slack

[ns] T − slack

[ns]

big:

1.4 ns

1.2 ns

1.0 ns

0.8 ns

0.7 ns

0.6 ns

0.4 ns

0.0 ns

Use the following ﬁgure to plot your results as an AT graphic and show them to an assistant.

600

700

800

900

1000

1100

1200

1300

1400

0.4 0.6 0.8 1 1.2

Area [GE]

Clock Period - Slack [ns]

1 2 ... 12 13 14 15 16 17 18 19 20

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