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4.2 Design Vision - Console

The Design Vision Console provides a facility to enter commands in textual form, this way linking the graphical user-interface

to the command line interface (i.e., the DC Shell). Furthermore, all commands entered by mouse buttons are echoed here

in correct syntax. The command window also reﬂects all information displayed by reports and menu windows.

Note: Some specialized commands are not available through the graphical user interface. They must be entered in

the Design Vision Console or in the DC Shell

To start the DC Shell in TCL mode use the cockpit with the DC Shell-xg-t option enabled.

4.3 Mouse Controls

The left mouse button is used to select one design object at a time. The middle mouse button is used to zoom. In the

display region use the right button to access the mouse menu. Among other things, the mouse menu is useful for zooming

the view.

4.4 Basic Synthesis Steps

Synthesis is a quite complex process, for which a more detailed explanation can be found in the VLSI textbook. Neverthe-

less, from a more abstract point of view, it can be subdivided into the following three main points:

Analyze Design: The analyze command converts the VHDL code into an intermediate format and stores it in a design

library (default: WORK ). Design libraries are the libraries you reference in VHDL using the library and use

statements. Once a design has been analyzed into a design library, it can be referenced from other (higher level)

designs. Special cases are VHDL packages, which have to be analyzed but not elaborated (they do not describe

designs).

Elaborate Design: The elaborate command reads a design unit from a design library into the SYNOPSYS DESIGN COM-

PILER memory. Referenced subdesigns are elaborated as well, if they can be found in the design library. For elab-

oration, VHDL generics can be set to their ﬁnal values (overriding default values deﬁned in the VHDL source code).

If you pass generics to an instantiated component in the VHDL code, the corresponding values will be propagated

to the subdesigns during elaboration. Generic values are appended to the base design name in SYNOPSYS DESIGN

COMPILER (an entity named adder will be named adder width8 if it has a generic width which is set to 8 ).

Compile Design: During the compilation process, the mapping of the generic logic and high level synthetic operators to

the available technology takes place. It can be initiated using the command compile_ultra.

Figure 5 shows optimization steps during compilation. In the ﬁrst step, some high level mappings and optimizations

are done if the design is read in high-level (RTL) VHDL (or Verilog). The next step involves general boolean optimiza-

tion. The logic can be ﬂattened (converted to two-level logic) or structured (multi-level logic), for example. The last

step includes mapping to the target library and optimization, e.g. using complex gates available in the target library.

At the end, design rules (fanout, . . . ) are ﬁxed and an area recovery step is performed.

Generic Netlist

Target Library

Constraints &

Attributes

Gate LevelArchitectural Level Logic Level

Combinational Mapping

Sequential Mapping

Design Rule Fixing

Flattening

Structuring

Resource sharing

Operator Re-Ordering

Implementation Selection

Optimized

Gate-Level

Netlist

Figure 5: Design optimization steps during compilation.

During the whole process, SYNOPSYS DESIGN COMPILER tries to attain the goals you set (you will learn setting these

goals, i.e., constraints, for the SYNOPSYS DESIGN COMPILER during this exercise). The constraints inﬂuence all the

steps involved. Setting timing constraints too tight will result in a large area. Per default, the SYNOPSYS DESIGN

COMPILER tries to fulﬁll the timing constraints ﬁrst, then the area recovery step tries to reduce the area without

introducing new timing violations. Tight constraints will also lead to much longer compile times, since the SYNOPSYS

DESIGN COMPILER only stops when the constraints are met or when there is no more improvement.

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